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Introduction to Physical Design
About the track
Description
In this track, students will acquire fundamental techniques and knowledge used at the physical implementation of integrated digital circuits at nanometer technology.
Track goal
The objective of this course is to provide the fundamental theoretical and practical tools to implement a
VLSI design, i.e. transforming a very simple HDL Design into a Physical Design that could be sent to the foundry for fabrication.
Prerequisites
This course is intended for advanced students, graduate students and professionals who have background on digital electronics – combinational circuits and sequential circuits – and CMOS technology – MOS transistor operation.
Contents
- Introduction to physical implementation
- Logical Synthesis
- Place and Route concepts
- Timing verification (Static Timing Analysis)
- Power consumption
- Implementation of a design using Open EDA tools
- Concepts of final verification
Professors
Eng. Fernando Tomás Segura Atencio (Marvell Technology Inc)
Fernando Segura Atencio was born in Córdoba, Argentina. He received the degree of Electronic Engineer from the National University of Córdoba, Argentina, in 2021. In November 2021, he joined Marvell Technology Inc. where he started working on the physical design of mixed-signal integrated circuits, working on different technology nodes, 5nm 3nm and 2nm, aiming at the lowest power digital design implementation. He has worked on the physical design of 800 Gb/s optical coherent transceivers and hard IP used in various projects.
Eng. Ivo Gay Caramuti (Marvell Technology Inc.)
He received the degree of Electronic Engineer from the National University of Córdoba in November 2024. In June 2024, he joined Marvell Technology Inc., where he initially worked as a Digital Design Intern on SSD storage architectures and controller‑level integrations. After completing his internship, he transitioned to a full‑time position as a Physical Design Engineer, focusing on the implementation of mixed‑signal integrated circuits in 5 nm, 3 nm, and 2 nm technology nodes. His work includes PPA optimization, placement, CTS and routing strategies, STA, PV, flow development, and contributions to tape‑outs of coherent optical transceivers and mixed‑signal IPs.
Since 2025, he has been a faculty member at the National University of Córdoba, teaching Digital Electronics, after having served three years as a teaching assistant. He participated in SERESSA, presenting a poster, and in EAMTA 2025, where he presented the paper “A First Mixed-Signal SoC for the CubeSAR‑UFSAT‑1 Mission CCD‑Payload.”
Resources
Preparation content
It is recommended that course participants join the WhatsaApp group https://chat.whatsapp.com/
Schedule
