Introduction to Physical Design

About the track

Description

In this track, students will acquire fundamental techniques and knowledge used at the physical implementation
of integrated digital circuits at nanometer technology

Track goal

The objective of this course is to provide the fundamental theoretical and practical tools to implement a
VLSI design, i.e. transforming a very simple HDL Design into a Physical Design that could be sent to the foundry for
fabrication.

Prerequisites

This course is intended for advanced students, graduate students and professionals who have
background on digital electronics – combinational circuits and sequential circuits – and CMOS technology
– MOS transistor operation

Contents

  1. Introduction to physical implementation
  2. Logical Synthesis
  3. Place and Route concepts
  4. Timing verification (Static Timing Analysis)
  5. Power consumption
  6. Implementation of a design using Open EDA tools
  7. Concepts of final verification

Professors

Ing. Alejandro Aguirre

Alejandro Aguirre was born in Corrientes, Argentina. He received the Electronic Engineer degree from the National University of Córdoba, Argentina, in 2011. In 2009, he joined ClariPhy Communications Inc. where he started working on high-speed analog circuit design and later moved to physical design of mixed signal integrated circuits. Then, in 2016, he joined Inphi Corporation which in 2020 was acquired by Marvell Technology where he still working as Physical Design Director. Along the years he was a key contributor in putting together implementation flows and developing “correct by construction” methodologies for Physical Design collaborating with multiple EDA vendors and different technology nodes from 65nm to 2nm, targeting lowest power digital design implementation, these flows and methodologies contributed to the success of complex “Coherent DSP” products line, reaching production quality on their A0 versions. He builds up a local physical design team from the scratch by training and mentoring young engineers. Since 2010, he has been working on the physical design of multiple generations of optical coherent transceivers at speeds of 10, 40, 100, 200, 400, 800 Gb/s and beyond

Resources

Preparation content

Schedule