Digital Design Adv.

About the track

Description

Track goal

  • Dar al estudiante el conocimiento sobre la problemática y las herramientas relacionadas al diseño de circuitos integrados de aplicación específica (ASIC), incluyendo los problemas relacionados al tiempo, optimización de rendimiento y potencia, y pruebas de verificación.
  • Que el estudiante comprenda la teoría y las herramientas involucradas en el diseño de sistemas digitales a gran escala de integración (VLSI) para arquitecturas con millones de transistores.
  • Que el estudiante aprenda a usar el Lenguajes de Descripción de Hardware para el diseño de sistemas digitales.
  • Que el estudiante comprenda las distintas métricas de Diseño: cantidad de dispositivos y área de implementación, velocidad de conmutación, disipación de energía y potencia.
 

Minimum content

  • Introducción al mundo digital y flujo de diseño de ASIC
  • Diseño de sistemas digitales mediante VerilogHDL
  • Máquinas de Estado Finito
  • Verificación funcional del diseño
  • Diseño orientado a satisfacer requerimientos de área, rendimiento y potencia
  • Implementación utilizando las herramientas de Synopsys (síntesis y place & route)

Professors

Dr. Víctor Grimblatt

Víctor Grimblatt is a microelectronics engineer from the Institut National Polytechnique de Grenoble (INPG – France) and an electronics engineer from the Universidad Técnica Federico Santa María (Chile). He holds a Ph.D. in IoT for Smart Agriculture from the IMS Laboratory at the University of Bordeaux. He is currently the Director and General Manager of the Synopsys Chile Innovation Center. He has experience and knowledge in business, technology, and trends in the electronics industry; therefore, he is often consulted for the development of new technology businesses.
He has published several articles on IoT, EDA, and embedded system development, and since 2007, he has been invited to various Latin American conferences (Argentina, Brazil, Chile, Mexico, Peru, and Uruguay) to speak about circuit design, EDA, IoT, and embedded systems. Since 2012, he has been the Chair of the Chilean IEEE CASS Chapter. He is also the President of the Chilean Association of the Electronics and Electrical Industry (AIE).
He has participated in several TCP conferences (ISCAS, ICECS, LASCAS) and chairs the Circuit Design and EDA Subcommittee of ICECS. He is also the Co-chair of the FoodCAS program. Since 2018, he has been the Chair of the LASCAS Steering Committee.

Ing. Ronald Valenzuela

Ronald Valenzuela currently leads a team of Product Engineers (PE) at Synopsys.
Together with his team, they provide support in Power Optimization and Power Analysis capabilities for the Synthesis and Place & Route tools.As a PE, they interact with customers to enable methodologies and also contribute to the planning and testing of the tools.
Ronald has over 10 years of experience in the EDA industry, holds an Electronic Engineering degree from the University of Concepción, and has a certification in Integrated Circuit Design from Stanford University, CA.

Ing. Esteban Viveros

Esteban Viveros is an Electronic Engineer from the University of Concepción (Concepción, Chile).
He started working at Synopsys in December 2013 as a Quality Engineer and is now an R&D Manager leading a team at the Chile Site.
The PV team is part of the Digital Design Group (DDG) and works on Product Validation for Synopsys tools used in RTL Synthesis, Testing, Physical Implementation (Place and Route), Formal Verification, and Signoff.
His team is responsible for the quality of the tools, focusing on stability, performance, usability, and QoR (Quality of Results).
The team interacts daily with colleagues and internal/external customers from different parts of the world (mainly the U.S., China, and Taiwan).
In addition, Esteban actively collaborates with Synopsys Chile’s university training activities.

Resources

Preparation content

Shared on SLACK EAMTA-CAE

Schedule