Basic Digital Design

About the track

Description

The course aims to teach the basic concepts of digital design. The learning process is divided into three phases.

Track goal

In the first part, the concepts of the HDL Verilog language are reviewed and the basic elements of digital design are presented: Combinational circuits and sequential circuits.
 
During the second part, the concepts of timing and gate and signal delays are addressed in order to understand how to properly design a digital circuit. The importance of a correct design is demonstrated, not only from the logic point of view, but also from the time domain, that is to make it work efficiently or, in our case, fast enough to satisfy the requirements of the application.
 
In the third part, a synchronous circuit will be simulated and implemented on an FPGA. During this process it will be verified that all constraints are met and finally its logic operation will be validated.

Minimum content

  • Introduction to Verilog.
  • Combinational and sequential circuits.
  • Binary, fixed point and floating point representation.
  • Time diagrams of combinational and sequential circuits.
  • Basic examples of hierarchical synthesis.
  • Temporal characterization of circuits.
  • Synchronous circuits and gate delay.
  • Characteristic times of an FF.
  • Implementation of basic circuits in FPGA.

Course Materials

Students are required to bring their own laptops.

Professors

Dr. Ing. Ariel Pola

(Celero Communication Inc. – Fulgor Foundation)

Ariel L. Pola received his degree in Telecommunications Engineering from the National University of Río Cuarto, Argentina, in 2008, and his Ph.D. in Engineering from the National University of the South, Bahía Blanca, Argentina, in 2016.
Since 2012, he has been a member of the organizing committee of the Argentine School of Micro- and Nanoelectronics, Technology, and Applications (EAMTA) and its associated conference, CAMTA, contributing to the promotion of micro- and nanoelectronics among undergraduate and graduate students in Argentina and across the region. Since 2013, he has also collaborated with the Fulgor Foundation, where he has been actively involved in training students in digital design applied to FPGA and ASIC technologies.
From 2009 to 2020, he worked at ClariPhy Argentina S.A. (later Inphi), where he contributed to the design and implementation of digital blocks for fiber-optic system-on-chip solutions supporting data rates from 10 Gbps to 600 Gbps.
Between 2022 and 2024, he served as an ASIC Radio Systems Designer at Ericsson in Sweden, focusing on the design and verification of components for high-speed mixed-signal platforms used in 5G mmWave radio products.
Since 2024, he has been Director of Design Engineering at Celero Communication Inc., where he leads the development of ASIC solutions for advanced fiber-optic communication applications.

Eng. Julian Giletta

(Celero Communication Inc.)

Eng. Julian Giletta was born in Córdoba, Argentina, in 1997. He received the Electronic Engineering degree from the Universidad Tecnológica Nacional, Facultad Regional Córdoba (UTN-FRC), Argentina, in 2020.
During his undergraduate studies, his strong interest in artificial intelligence led him to actively participate for three years in research and development projects related to artificial intelligence applied to industrial systems at the Centro de Investigación en Informática para la Ingenieria (CIII-UTN).
Since 2021, he has been working professionally in the field of digital design. Between 2021 and 2022, he worked at INVAP, contributing to the development of satellite and defense technologies, with a focus on complex electronic and digital systems.
From 2023 to 2025, he worked at indie Semiconductor (INDI), a technology company that designs and supplies high-performance semiconductor and software solutions for the automotive industry. The company focuses on Advanced Driver-Assistance Systems (ADAS), autonomous vehicles, connected vehicle cabins, and electrification. During this period, he was involved in the development and integration of digital hardware solutions for automotive safety and perception platforms.
In mid-2025, he joined Celero Communications, a U.S. technology startup specializing in advanced coherent Digital Signal Processing (DSP) solutions. At Celero, he is part of the digital design team, contributing to the development of chips and platforms for high-bandwidth, low-power optical connectivity within Artificial Intelligence (AI) infrastructure, with the goal of efficiently interconnecting large-scale AI data centers over long distances.

Resources

Preparation content

Shared on SLACK EAMTA-CAE

Schedule