Hands On FPGA

About the track

Description

Every machine instruction in a Computer System is solved through a sort of micro-operations that use very different low level hardware resources depending on the processor range and instruction type. These low-level resources are normally known as Computer Computer or Computer Microarchitecture, and its knowledge allows us to face real Hardware projects in every development stage: Description, modeling, simulation, and finally, Integrated Circuit Design (SoCs, ASICs, etc.). Very active, broad, and innovative Research areas related with Computer Systems Organización can be found, some of whose results, several years after their publication, lead to innovative new Processors, memory technologies, or hardware controllers that build a Computer System. Is it possible to get a job in the Custom Computer Systems design industry? Of course!. The rise of architectures such as RISC-V offer a Big opportunity for this. Its specifications are focused exclusively on Architectural resources, leaving the Organization decision to the hardware designer, who can adapt this architecture to a modest closed-loop control system or to multiple processing cores with Cache memories, memory virtualization capacity, out of order execution, and so on. In this way, the performance can be increased by providing custom solutions in the SoC architecture. A Big enough international market is waiting for innovations. A foundry is not required for this purpose. You only need adequate development tools, and some powerful computers. But without knowing the basics and fundamentals, that rules the building blocks that work under Architectural registers and instructions, there is not much that you can do in this field.

Track goal

Taking into account this opportunity, this Workshop is intended for those interested in learning these basic fundamentals of microarchitecture in order to join a Research or development team with something more to offer than an IDE, C programming and development resources for applications skills.  It is desirable to have some processor architecture knowledge (x86, ARM, or RISC-V preferably), and notion-basic skills on some HDL, and FPGA.

Prerequisites

It is desirable to be familiar with some processor arquitecture (x86, ARM, or RISC-V preferably), have notions of HDL and FPGA.

Minimum content

The course is organized in theoretical sessions and Laboratory sessions to solve some implementation blocks.

  1. SoC introduction.
  2. Microarchitecture Basis
  3. Memory Subsystem. Cache and DRAM. Hierarchy
  4. Instruction Level Parallelism
  5. Data Level Parallelism
  6. Speculative Out Of Order Execution

Professors

Esp. Ing. Alejandro Furfaro (UTN-FRBA)

Born in Bs. As. Received his degree of Electronic Engineer in Facultad Regional Buenos Aires of Universidad Tecnológica Nacional, and post graduate as Telecommunications Management Specialist in Universidad de San Andrés. Currently he works in his PhD Thesis in Computer Science at Facultad de Ciencias Exactas y Naturales of Universidad de Buenos Aires. He is Titular Professor in Electronic Department of Universidad Tecnológica Nacional, (where he was Chair between 2006 and 2018), and Associate Professor at Computer Department of Facultad de Ciencias Exactas y Naturales of Universidad de Buenos Aires. He is the Director of Digital Processing Laboratory At Electronic Department of Universidad Tecnológica Nacional Facultad Regional Buenos Aires. 

Ing. Roberto Simone (UTN-FRBA)

Born in Bs. As. Received his degree of Electronic Engineer in Facultad Regional Buenos Aires of Universidad Tecnológica Nacional. He has been working for 20 years in the field of embedded systems. He is Professor in Electronics Department of Universidad Tecnológica Nacional. He is also a researcher in the area of asynchronous digital circuits at the Universidad Tecnológica Nacional Facultad Regional Buenos Aires.

Dr. Ing. Luciano Ferreyro (UTN-FRBA)

Born in Buenos Aires, Argentina, he received his degree in Electronic Engineering from the Facultad Regional Buenos Aires at the Universidad Tecnológica Nacional (UTN-FRBA). In 2023, he was awarded a double-doctoral degree in Engineering through a cotutelle program between the Universidad Nacional de San Martín (Argentina) and the Karlsruher Institut für Technologie (Germany). Since 2014, he has worked as a teaching assistant in the Electronics Department at the Universidad Tecnológica Nacional. That same year, he began his research career at the Instituto de Tecnologías en Detección y Astropartículas (ITeDA), where he contributed to the Pierre Auger Observatory. For his Ph.D., he participated in the Q&U Bolometric Interferometer for Cosmology (QUBIC) project for the UNSAM side, and the Electron Capture in Holmium (ECHo) experiment for the KIT side, developing and implementing the digital backend of the readout electronics for cryogenic detectors multiplexed in the frequency domain via a microwave superconducting quantum interference device (SQUID) multiplexer (μMux). He also carries out research at the Digital Processing Laboratory of UTN-FRBA. Currently, he holds a postdoctoral position at ITeDA through CONICET. His research interests include digital signal processing, the design and implementation of readout electronics architectures, and the development of cryogenic quantum detector technologies.

Dr. Ing. Yao Ming Kuo (UTN-FRBA)

Received the Engineer degree in Electronic Engineering (2018) from Universidad Tecnológica Nacional (UTN Argentina) in 2018 and the Ph.D. international degree in computer engineering from Universidad Antonio de Nebrija (Spain) in 2022. He has previously worked as researcher at UTN and as hardware design engineer at INTI (National Institute of Industrial Technology, Argentina) in the micro- and nanoelectronics department. He has designed ASICs, FPGAs, and microcontroller-based systems for instrumentation sensors and power-save applications at INTI for third-party companies.

During his academic career, he obtained multiple scholarships for studies in Germany through DAAD (German Academic Exchange Service), as well as the Banco Santander Scholarship to carry out his Ph.D. degree at Universidad Antonio de Nebrija (Madrid, Spain) and a research stay at University College Dublin (Dublin, Ireland).

He is currently working as a SoC Digital Design Engineer consultant at Monolithic Power Systems (MPS). His interest areas include digital signal processing, SoCs, computer architecture, digital design and implementation, fault-tolerant systems, and reliability.

Resources

Preparation content

Schedule