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Basic Digital Design
About the track
Description
The course aims to teach the basic concepts of digital design. The learning process is divided into three phases.
Track goal
In the first part, the concepts of the HDL Verilog language are reviewed and the basic elements of digital design are presented: Combinational circuits and sequential circuits.
During the second part, the concepts of timing and gate and signal delays are addressed in order to understand how to properly design a digital circuit. The importance of a correct design is demonstrated, not only from the logic point of view, but also from the time domain, that is to make it work efficiently or, in our case, fast enough to satisfy the requirements of the application.
In the third part, a synchronous circuit will be simulated and implemented on an FPGA. During this process it will be verified that all constraints are met and finally its logic operation will be validated.
Minimum content
Introduction to Verilog.
Combinational and sequential circuits.
Binary, fixed point and floating point representation.
Time diagrams of combinational and sequential circuits.
Basic examples of hierarchical synthesis.
Temporal characterization of circuits.
Synchronous circuits and gate delay.
Characteristic times of an FF.
Implementation of basic circuits in FPGA.
Professors
Dr. Ing. Ariel Pola (Ericsson-Fundación Fulgor)
Dr. Ing. Ariel L. Pola (Ericsson-Fundación Fulgor) was born in Rio Cuarto, Argentina, in 1983. He received the Telecommunication Engineer degree from the Universidad Nacional de Río Cuarto, Argentina, in 2008 and his Ph.D degree in engineering from the Universidad Nacional del Sur, Bahia Blanca, Argentina from 2016.
In 2009 he obtained a doctoral scholarship from the National Agency for the development of his thesis on “Reduced Complexity Architectures for Electronic Compensation Dispersion in High Speed Communications Systems” and in 2016 obtained the title of PhD in Engineering from the Universidad Nacional del Sur.
Since 2012, it has actively participated in the organization of the Argentine School of Micro-Nanocelectronics, Technology and Applications (EAMTA) and its associated CAMTA conference, whose objective is to promote the area between undergraduate and graduate students of the country and the region.
Between 2013 and 2015, he collaborated in Fundación Fulgor in the development of a prototype for a Satellite Proximity-1 Modem for the SARE’s mission to the Comisión Nacional de Actividades Espaciales (CONAE).
During 2009 to 2020 he collaborated in ClariPhy Argentina SA (Inphi) in the design and implementation of digital blocks for generations of chips for fiber optic systems from 10 Gbps to 600 Gbps.
In 2020 he founded and coordinates activities at CognitionBI, which aims to offer multi platform development services (GPU, FPGA, ASIC) in areas such as optical communications, satellite communications, microelectronics, signal processing, image processing, internet of things, automatic control, artificial intelligence and machine learning.
In 2022, he took up the position of radio ASIC system designer at Ericsson (Sweden), where he designs and verifies components of the high-speed mixed-signal platform. This platform is an integral part of Ericsson’s 5G mmWave radio product.
Eng. Federico G. Zacchigna (FIUBA)
Eng. Federico G. Zacchigna (FIUBA) was born in Buenos Aires, Argentina, in 1987. He received his tı́tulo de Ingenieron Electrónico from the University of Buenos Aires, Argentina, in 2012. He is currently completing a PhD in Electronic Ingernierı́a at UBA under the topic of “Study, analysis and development of consensus algorithms for wireless sensor networks”. Since 2019 he is the director of the Embedded Systems Laboratory at UBA. Since 2012 he has been teaching in the Master in Embedded Systems (MSE) and in the Carrera de Especializacion en Sistemas Embebidos (CESE), both at UBA. Since 2009 he has been teaching at the Electronic Engineering course at UBA, currently holding an Adjunct Professor position and a Head of Practical Works position. Since 2013 he has taught several courses in the areas of FPGA and Digital Signal Processing. Between 2012 and 2015 he performed Independent Verification and Validation work for the National Commission of Space Activities (CONAE) and the company SpaceSur, related to the SAOCOM satellite project. Since 2014 he is actively researching on topics related to digital design on FPGA and ASIC, Signal Processing, Digital Signal Processing and Communications.
Resources
Preparation content
Shared on SLACK EAMTA-CAE
Schedule
