Jennifer Blain Christen

Arizona State University

Tuesday March 5 18:00-19:00

“Fully-passive Neural Stimulation and Recording”


Jennifer Blain Christen received her doctorate in electrical and computer engineering from Johns Hopkins University in 2007, followed by a postdoctoral fellow at the Johns Hopkins School of Medicine in the Immunogentics Department. Blain Christen is currently an associate professor of electrical engineering at Arizona State University in the Center for Bioelectronics and Biosensors at the Biological Design Institute. The group has recently focused on point-of-care diagnostics and flexible neural interfaces.

She is an NSF CAREER awardee, Fulton Entrepreneurial Professor, Palais Distinguished Faculty Scholar, and Flinn Foundation Translational Bioscience Awardee. Blain Christen serves on the Board of Governors for the IEEE Circuits and Systems Society, and she is past president of the Biomedical Circuits and Systems Technical Committee.

Andreas G. Andreou

Johns Hopkins University

Monday March 6 18:00-19:00

“Neurochiplets and Silicon Brains in 3D CMOS”

The brain is without doubt the world’s most powerful computer for solving problems in machine perception (vision, speech, language) and machine learning. Brains exist in 2+delta -dimensional physical space yet are capable of efficiently solving problems in higher dimensional spaces. We believe that the network structure of the brain architecture in 2+delta dimensional space contributes significantly to its effectiveness and energy efficiency in cognition. At all levels of the central nervous system, from retina to the cortex, the tissue is organized in a hierarchy of layers. In certain layers there is an abundance of axons, the physical structures in neurons responsible for communication” while others are densely packed with cell bodies and dendrites, or what one will consider as the computational” structures in the tissue. Furthermore, the layers are tightly coupled vertically through what is termed in biology a column”. Over the last half century computer scientists, architects and engineers have envisioned building computers that match the parallel processing capabilities of biological brains for perception and cognitive computing.

Three-dimensional integration through wafer stacking and 2.5D assembly is an alternative to technology scaling and monolithic integration that achieves increase in the number of transistors and short-range interconnect per unit area thus improving energy efficiency. To addres the challenges of rapid and flexible prototyping of large bioinspired systems for cognitive computing we abstract the 2+delta brain architectonics provide a guidance towards future development of silicon integrated systems for machine perception and learning that would be as effective and as efficient as biological brains. Neurochiplets SOC 2.5D architecture relies on this alternative approach to scaling, driven primarily by cost and flexible and rapid system level integration. 2.5D integration on a silicon interposer will interface the memory to neuromorphic chiplets and a commodity FPGA and processors (RISC-V) for operating system support and data I/O. In this talk I will discuss the design of three generations of bio-inspired 3D CMOS SOCs designed over a period of 15 years. I will present experimental data from the architectures and discuss successes and failures.


Andreas G. Andreou is a professor of electrical and computer engineering, computer science and the Whitaker Biomedical Engineering Institute, at Johns Hopkins University. Andreou is the co-founder of the Johns Hopkins University Center for Language and Speech Processing. Research in the Andreou lab is aimed at brain inspired microsystems for sensory information and human language processing. Notable microsystems achievements over the last 25 years, include a contrast sensitive silicon retina, the first CMOS polarization sensitive imager, silicon rods in standard foundry CMOS for single photon detection, hybrid silicon/silicone chip-scale incubator, and a large-scale mixed analog/digital associative processor for character recognition. Significant algorithmic research contributions for speech recognition include the vocal tract normalization technique and heteroscedastic linear discriminant analysis, a derivation and generalization of Fisher discriminants in the maximum likelihood framework. In 1996 Andreou was elected as an IEEE Fellow, “for his contribution in energy efficient sensory Microsystems.”


Haas, David

Allegro Microsystems

Thurdasy March 7 18:00-19:00

“The Role of AI and LLM’s in Modern Mixed Signal IC Development ”


Jamie started his career as an analog design engineer at National Semiconductor, where he began his journey over two decades ago. He has cultivated a distinguished career in IC design and his 18-year tenure at Allegro Microsystems is a testament to his deep passion in designing and leading state of the art magnetic sensor IC’s. A brief foray into the AI startup scene with AIStorm showcased his versatility and forward-thinking approach where he and the team showcased first silicon at CES in Las Vegas, before returning to Allegro as a Technology Fellow. Here, Jamie combines a multi-dimensional background in analog, digital and software with cutting-edge AI, championing innovations that bridge the past and future of mixed-signal IC design. Grounded by his history yet always looking to the horizon, Jamie’s passion for technology is matched only by his commitment to his family and a future of lifelong learning.

Pamela A. Abshire

University of Maryland, College Park

Thursday March 7 9:03-10:45

"Lab on CMOS Capacitance Imagers to Monitor Living Cells"

One of the great successes of microelectronics in the last few decades has been increasing miniaturization and integration with different applications, which produces a steady stream of new applications, new innovations, and new products. An emerging research area that leverages information technology advances for new applications is lab-on-CMOS (LoCMOS) systems, highly integrated, multiphysics microsystems that place instrumentation in intimate contact with sensing and actuation capabilities. This talk will provide a brief overview of LoCMOS systems, the technologies used to construct them, and also review the standing technical challenges of integrating them into biomedical devices, including packaging, surface fouling, sterilization, communication, and system power. This talk will provide a detailed introduction to the history and current developments in capacitance imagers, a completely novel measurement that cannot be performed using traditional approaches. Current generations of capacitance imagers have demonstrated unprecedented spatial and temporal resolution for measurements of the surface attachment of living cultured cells. By establishing dense and information-rich interfaces with cultured cells, capacitance imaging offers the potential for disruptive changes in biosensing and medical diagnostics in the near future


Pamela Abshire is a Professor in the Department of Electrical and Computer Engineering and the Institute for Systems Research at the University of Maryland, College Park. She received the BS in physics from CalTech in 1992, and the MS and PhD in electrical and computer engineering from Johns Hopkins in 1997 and 2002. She is internationally known for her work in low power mixed-signal integrated circuits (IC), adaptive ICs and IC sensors, and CMOS biosensors. Her research focuses on better understanding and exploiting the tradeoffs between performance and resources in natural and engineered systems, including hybrid devices incorporating CMOS, MEMS, optoelectronics, microfluidics, and biological components. Her honors include an NSF CAREER award (2003), elevation to IEEE Fellow (2018) for contributions to CMOS biosensors, and recognition as a Distinguished Scholar-Teacher at the University of Maryland (2021). She previously served on the Emerging Technologies and Research Advisory Committee for the U.S. Department of Commerce (2008-2018), on the Board of Governors for the IEEE Circuits and Systems Society (2013-2018), the IEEE Fellow Committee (2019-2021), as General Co-Chair for the 2017 IEEE International Symposium on Circuits and Systems, on the Microsystems Exploratory Council for the DARPA Microsystem Technology Office, and as General Co-Chair for the IEEE International Midwest Symposium on Circuits and Systems 2023. She just started a new term (2024-2026) as a Member at Large on the Board of Governors for the IEEE Circuits and Systems Society.

Ariel L. Pola

Ericsson-Fundación Fulgor

Friday March 8 17:00-17:45

"5G mmWave Applications: Basic Concepts and Verification"

The fifth generation of wireless technology, commonly known as 5G, brings forth a revolutionary leap in communication capabilities, and one of its key components is millimeter wave (mmWave) technology. 5G mmWave operates in frequency bands above 24 GHz, offering significantly higher data rates and low latency compared to previous generations. This enables a wide range of applications, including ultra-fast internet browsing, augmented and virtual reality experiences, autonomous vehicles, and the Internet of Things (IoT).
However, the implementation and optimization of 5G mmWave technology pose unique challenges due to the characteristics of mmWave signals, such as increased susceptibility to blockage and limited propagation distance. Therefore, thorough performance verification is crucial to ensure the reliability and efficiency of 5G mmWave systems.
Field Programmable Gate Arrays (FPGAs) emerge as valuable tools for verifying the performance of 5G mmWave systems. FPGAs are versatile hardware devices that can be reconfigured to emulate specific functionalities of digital circuits. Their flexibility allows engineers to prototype and test complex algorithms, communication protocols, and signal processing techniques in a hardware environment.
In this tutorial we will explore the basic concepts of 5G mmWave, its applications and how FPGAs are used in design verification.


Dr. Ing. Ariel L. Pola (Ericsson-Fundación Fulgor) was born in Rio Cuarto, Argentina, in 1983. He received the Telecommunication Engineer degree from the Universidad Nacional de Río Cuarto, Argentina, in 2008 and his Ph.D degree in engineering from the Universidad Nacional del Sur, Bahia Blanca, Argentina from 2016.
In 2009 he obtained a doctoral scholarship from the National Agency for the development of his thesis on “Reduced Complexity Architectures for Electronic Compensation Dispersion in High Speed Communications Systems” and in 2016 obtained the title of PhD in Engineering from the Universidad Nacional del Sur.
Since 2012, it has actively participated in the organization of the Argentine School of Micro-Nanocelectronics, Technology and Applications (EAMTA) and its associated CAMTA conference, whose objective is to promote the area between undergraduate and graduate students of the country and the region.
Between 2013 and 2015, he collaborated in Fundación Fulgor in the development of a prototype for a Satellite Proximity-1 Modem for the SARE’s mission to the Comisión Nacional de Actividades Espaciales (CONAE).
During 2009 to 2020 he collaborated in ClariPhy Argentina SA (Inphi) in the design and implementation of digital blocks for generations of chips for fiber optic systems from 10 Gbps to 600 Gbps.
In 2020 he founded and coordinates activities at CognitionBI, which aims to offer multi platform development services (GPU, FPGA, ASIC) in areas such as optical communications, satellite communications, microelectronics, signal processing, image processing, internet of things, automatic control, artificial intelligence and machine learning.
In 2022, he took up the position of radio ASIC system designer at Ericsson (Sweden), where he designs and verifies components of the high-speed mixed-signal platform. This platform is an integral part of Ericsson’s 5G mmWave radio product.