This talk presents key findings from two PhD research projects focused on energy-efficient neural network processing through event-based vision and simplicial architectures.
The first part covers event-based vision sensors, inspired by the human retina, which capture only scene changes to reduce data and energy consumption. A custom SoC utilizing content-addressable memory (CAM) was developed to efficiently process event-driven CNNs, enabling real-time applications in robotics and autonomous systems.
The second part explores simplicial processing units, an alternative to traditional convolutional layers. The research introduced the Channel-Specific Symmetric Simplicial (ChSymSim) model, improving network flexibility and efficiency. Multiple SoCs were fabricated, featuring optimized architectures and low-power designs, enhancing AI applications for embedded systems.
These efforts contribute to advancing AI hardware with biologically inspired and computationally efficient solutions.
Biography:
Pedro Julián is an Electronic Engineer, graduated from Universidad Nacional del Sur (UNS), Bahía Blanca, Argentina, in 1994, and holds a PhD in Systems Control from the same university (1999). He has served as an Associate Professor at Johns Hopkins University, USA and as Principal Investigator at CONICET. He is currently Head of the Allegro Design Center in Bahía Blanca and an Associate Professor at UNS. He has published five books, co-edited 13 conference proceedings, co-authored four patents, and over 40 articles in top international journals.
Pedro has supervised 15 PhD and 5 master’s theses and led several national research projects funded by agencies such as the National Agency for Scientific and Technological Promotion. He has received multiple awards, including the MINCyT Bernardo Houssay Award (2009) and the Engineering Award of the National Academy of Natural, Physical and Exact Sciences (2010), among others.
He is one of the founding members of the Argentine School of Micro and Nanoelectronics (EAMTA), offering training and education in integrated circuit technology since 2007.
This talk will present a brief overview of advances in ferroelectric devices and their integration into computing systems to provide novel functionality and energy efficiency in various data intensive applications. The talk will emphasize on cross-stack design opportunities in designing stacked intelligent 3D memory systems. The talk will cover circuit and architectural features leveraging the non-volatile properties of ferroelectric devices for hardware obfuscation, accelerator designs and in-memory compute structures.
Biography:
Vijaykrishnan Narayanan is an Evan Pugh University Professor and Robert Noll A. Chair Professor of Computer Science and Engineering and Electrical Engineering at The Pennsylvania State University. He is a Fellow of ACM, IEEE, AAAS and the National Academy of Inventors. He serves as associate director of DoE 3DFeM center, thrust lead for DARPA/SRC PRISM center, associate Editor-in-Chief of IEEE Micro, the academic coordinator for the India-US Defense Acceleration Ecosystem and Associate Executive Director of AI for GeoEd foundation.
Thin dielectric films are essential components of most micro- and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO2, HfO2, and Al2O3), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new-concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.
One of the great successes of microelectronics in the last few decades has been increasing miniaturization and integration with different applications, which produces a steady stream of new applications, new innovations, and new products. An emerging research area that leverages information technology advances for new applications is lab-on-CMOS (LoCMOS) systems, highly integrated, multiphysics microsystems that place instrumentation in intimate contact with sensing and actuation capabilities. This talk will provide a brief overview of LoCMOS systems, the technologies used to construct them, and also review the standing technical challenges of integrating them into biomedical devices, including packaging, surface fouling, sterilization, communication, and system power. This talk will provide a detailed introduction to the history and current developments in capacitance imagers, a completely novel measurement that cannot be performed using traditional approaches. Current generations of capacitance imagers have demonstrated unprecedented spatial and temporal resolution for measurements of the surface attachment of living cultured cells. By establishing dense and information-rich interfaces with cultured cells, capacitance imaging offers the potential for disruptive changes in biosensing and medical diagnostics in the near future
Biography:
Pamela Abshire is a Professor in the Department of Electrical and Computer Engineering and the Institute for Systems Research at the University of Maryland, College Park. She received the BS in physics from CalTech in 1992, and the MS and PhD in electrical and computer engineering from Johns Hopkins in 1997 and 2002. She is internationally known for her work in low power mixed-signal integrated circuits (IC), adaptive ICs and IC sensors, and CMOS biosensors. Her research focuses on better understanding and exploiting the tradeoffs between performance and resources in natural and engineered systems, including hybrid devices incorporating CMOS, MEMS, optoelectronics, microfluidics, and biological components. Her honors include an NSF CAREER award (2003), elevation to IEEE Fellow (2018) for contributions to CMOS biosensors, and recognition as a Distinguished Scholar-Teacher at the University of Maryland (2021). She previously served on the Emerging Technologies and Research Advisory Committee for the U.S. Department of Commerce (2008-2018), on the Board of Governors for the IEEE Circuits and Systems Society (2013-2018), the IEEE Fellow Committee (2019-2021), as General Co-Chair for the 2017 IEEE International Symposium on Circuits and Systems, on the Microsystems Exploratory Council for the DARPA Microsystem Technology Office, and as General Co-Chair for the IEEE International Midwest Symposium on Circuits and Systems 2023. She just started a new term (2024-2026) as a Member at Large on the Board of Governors for the IEEE Circuits and Systems Society.
The quickly growing demand for computational power required to develop and operate
advanced artificial intelligence models, fueled by an unending desire for information access
anytime and anywhere, is using up large quantities of energy, depleting Earth’s resources, and
worsening climate change rapidly. Motivated by the effectiveness, efficiency, and robustness of
natural intelligence in biological information processing systems, neuromorphic engineering
provides viable options for extremely low-energy cognitive computing in highly parallel
distributed architecture. The emergence of nanoscale memristors, combined with
neuromorphic hardware, raised hopes of being able to build CMOL (CMOS/nanowire/molecular)
type ultra-dense in-memory-computing circuit architectures by fabricating lower density
neurons on CMOS and placing massive analog synaptic connectivity with nanowire and
nanoscale-memristor fabric post-fabricated on top. Currently available hybrid CMOS-memristor
technologies allow to implement large-scale neuromorphic systems with dense memristive
crossbars. These memristive devices are especially suited to implement online learning
algorithms like Spike-Timing-Dependent Plasticity (STDP).
Biography:
Luis A. Camuñas Mesa is an Electronic Engineer from the University of Seville, Spain (2003), and holds a PhD in event-based vision systems from the same university (2010). In 2006, he was a Visiting Student with the Institute of Neuroinformatics, Zürich (Switzerland). From 2010 to 2013, he was an Associate Post-Doctoral Researcher with the Centre for Systems Neuroscience, University of Leicester (UK), where he was involved in olfactory sensing and processing, spike detection and sorting, and simulation of extracellular recordings. In 2013, he received the ‘Juan de la Cierva’ Post-Doctoral Fellowship at the Institute of Microelectronics of Seville (IMSE-CNM). In 2019, he became a Research Associate at the University of Seville. Since 2023, he holds a position as Tenured Scientist at CSIC (Spanish National Research Council). His current research interests include bioinspired circuits and systems, real-time event-based vision sensing and processing chips, neuromorphic stereo vision, and nanoscale memristor-based AER circuits for STDP learning. He has been an Associate Editor of the IEEE Transactions of Circuits and Systems – II: Express Briefs.