Industrial Track

About the track


The industrial track is an space where several independent workshops or tutorials are given by the industry representants. The assistants can assist to one or several activities.

Companies and Institutions

      • Fulgor Tarpuy
      • NYTT
      • Synopsys Chile
      • Indie
      • Marvell 
      • Allegro

Track goal

This track is aimed to bring to the participants to real industry processes, design flows and tools. It is composed of a grid of not correlated tutorials and workshops, provided by our sponsors, so the participants can choose to assist to one or several of them. Furthermore, they are not overlapped with CAE, being specially designed for those that assist to the Conference, but not take any of the classic tracks.


Leandro Borgnino et al.

Fundación Fulgor/Tarpuy

Monday March 6 9:00-13:00

"Advanced Telecommunications and Autonomous Navigation Workshop for Engineering and Doctoral Training"

In this workshop, participants will learn about digital and analog processing techniques and how to apply them in autonomous navigation and digital communications. Participants will have the opportunity to work on real-life autonomous navigation simulations using LiDAR data and get hands-on digital communication simulation tools. As a demonstration, some analog implementations are going to be exposed.
The workshop is designed for professionals and researchers in digital communications, robotics, autonomous systems, and data science.

Federico Paredes &
Tomas Prudente

indie Argentina

Monday March 6 14:00-17:30

"Design and Verification of an FFT Accelerator"

The ever-evolving field of advanced driver assistance systems (ADAS), particularly within LiDAR and RADAR applications, demands precise and accurate digital signal processing (DSP) capabilities that help alleviate the processing load from the CPU. In this workshop, we delve into the realm of DSP algorithms, with the ubiquitous fast fourier transform (FFT) taking center stage. We will explore the system design approach, through hands-on RTL implementation, culminating with digital verification using the cutting-edge Cocotb tool. Don’t miss out on this opportunity to elevate your design and verification skills to the next level.

Alejandro Pasciaroni & Kevin Viglianco


Tuesday March 7 9:00-13:00

"Static Time Analysis (STA) and PeakRDL tool. An overview of methodologies for digital design and verification improvement"

Static Timing Analysis (STA) is crucial for the timing analysis and final sign-off of modern digital IC designs. It helps front-end engineers in RTL design to take into account implementation limitations while designing logic or collaborating with other design blocks. On the other hand, STA is a mandatory skill for back-end engineers involved in physical implementation.Nowadays, with the exponential increase of ASICs’ complexity, it is crucial to have the appropriate methods to ensure an optimal design. The main objective is to give an introduction to the following independent approaches aimed at both design and verification processes. STA is a crucial methodology for timing analysis and final sign-off of modern digital IC designs. It helps front-end engineers in RTL design to take into account implementation limitations while designing logic or collaborating with other design blocks. On the other hand, STA is a mandatory skill for back-end engineers involved in physical implementation. PeakRDL tool is a toolchain that unifies many aspects of register automation using SystemRDL register description language. It allows the automatic generation of multiple accurate views, like synthesizable SystemVerilog RTL register blocks, dynamic HTML documentation, and UVM register model abstraction layer. 

Nestor Campos &
Agustin Martino

Marvell Argentina

Tuesday March 7 14:00-17:30

"A practical approach to the resolution of Communications Systems problems using Digital Signal Processing (DSP)"

We will quickly share Marvell’s workflow in the field of digital communications and then we will go into the analysis of the most common problems in the industry. A typical optical channel problem (carrier offset between the transmitting laser and the local oscillator) will be shown and the solution will be analyzed from a theoretical point of view: carrier recovery using a DPLL (Digital Phase Locked Loop) assisted by decisions. Secondly, an electronic circuit reflecting the mathematical operations of the theoretical solution will be developed. And finally, some of the parameters of the implemented circuit will be analyzed, such as latencies, quantization, and algorithmic simplifications. The development of this workshop will be live on a whiteboard where the attendees will be able to interact and contribute to the solutions. In addition, computer simulations will be performed in real-time to complement the development on a whiteboard.

Víctor Grimblatt

Synopsys Chile

Wednesday March 8 9:00-13:00

"Digital IC Design Flow – From the Idea to the Chip"

The design of a digital IC design goes through different steps, design flow, and uses a variety of tools that are needed to ensure the success of the design. Nowadays, with designs that have a few billions of transistors, it is almost impossible to design a digital IC design without using Electronic Design Automation (EDA) tools. This tutorial will analyze the digital IC design flow detailing each step of the flow. It will also cover the tools that are needed in each step and how the design methodology has evolved based on the used technology.

Daniel E. Musciano et al.

Allegro Microsystems Argentina

Wednesday March 8 14:00-17:30

"Designing an IC: From Initial Idea to Final Product"

The Core Development of an IC Product involves a well synchronized interaction of silicon implementation teams such as Analog and Digital Design, Layout and Verification and critical supporting ones like System Engineering, Product Evaluation, Devices Modeling, Fab and EDA tools to name a few.
Understanding the role of engineers within each group is of fundamental importance to new engineers coming to our industry to better shape their careers.
A real and recent development of Allegro South America Design Center will be used as a case study to present the methodologies in a practical way.
Allegro managers Juan Cesaretti (Analog), Octavio Alpago (Digital), Andres Kasulin (Modeling) and Daniel Musciano (Layout) will present the material and be available for Questions from the audience.