Electronic Packaging

IMPORTANT NOTICE REGARDING THE COURSE SCHEDULE

Due to the availability of the instructors, the Electronic Packaging course will be held only on Wednesday.

Participants who arrive earlier may contact instructors from other courses to attend as auditors, subject to availability, or join the course directly starting on Wednesday.

About the track

Description

Basic Semiconductor Packaging Course

  • Title: Introduction to Chip Packaging
  • Instructor: Annette Teng
  • Duration: 2 hours
  • Description: Introductory course covering the process from the fabricated wafer to the packaged chip. It includes wafer thinning, wafer dicing, die attach, wire-bond interconnection, and encapsulation, along with quality control techniques.

Advanced Packaging Course

  • Title: Advanced Packaging
  • Instructor: John Lau
  • Duration: 2+ hours
  • Contents: Advanced course covering flip-chip, fan-out and fan-in wafer-level packaging, Cu–Cu hybrid bonding, co-packaged optics, glass packaging, and best-practice recommendations.

Track goal

1. Electronic Packaging of Semiconductor Chips Course.

2. Additive Printing for electronic applications Course.

3.⁠ ⁠Electronic Package Supply Chain Course.

In the first part, the concepts of the HDL Verilog language are reviewed and the basic elements of digital design are presented: Combinational circuits and sequential circuits.
 
During the second part, the concepts of timing and gate and signal delays are addressed in order to understand how to properly design a digital circuit. The importance of a correct design is demonstrated, not only from the logic point of view, but also from the time domain, that is to make it work efficiently or, in our case, fast enough to satisfy the requirements of the application.
 
In the third part, a synchronous circuit will be simulated and implemented on an FPGA. During this process it will be verified that all constraints are met and finally its logic operation will be validated.

Minimum content

  • Introduction to Verilog.
  • Combinational and sequential circuits.
  • Binary, fixed point and floating point representation.
  • Time diagrams of combinational and sequential circuits.
  • Basic examples of hierarchical synthesis.
  • Temporal characterization of circuits.
  • Synchronous circuits and gate delay.
  • Characteristic times of an FF.
  • Implementation of basic circuits in FPGA.

Course Materials

Students are required to bring their own laptops.

Professors

Eng. Annette Teng

Eng. Annette Teng is Director of Package Integration at AIM Photonics TAP Facility in Rochester, New York.  She received her PhD from University of Virginia in Materials Engineering.  She was previously the Chief Technology Officer at Promex Industries, a manufacturer of electronic and medical components in Silicon Valley, since 2014.  She has spent most of her career in electronic component packaging and manufacturing in both corporate and academic environments.   She has worked in components packaging and assembly at Signetics (now Philips Semi), Linear Technology Corp. (now Analog Device) Corwil Technology (now Micross).  Prior to joining Promex, she was Package Assembly Manager at Silanna in Australia for 3 years.   She also worked at Hong Kong University of Science and Technology and helped launch their electronics packaging programs from 1997 to 2000.  She has published at ECTC and Meptec in the field of dicing, die attach films and package delamination.  She has been active in IEEE Electronic Packaging Society Chapter activities in Silicon Valley since 2000 and was the Chapter Chair for multiple years.  She is currently Regional Director of Region 1-7 and 9 for IEEE EPS.

Eng. John Lau

Eng. John Lau with more than 40 years of R&D and manufacturing experience in semiconductor packaging, has published more than 530 peer-reviewed papers (385 as the principal investigator), 52 issued and pending US patents (31 as the principal inventor), and 25 textbooks. He has been actively participating in industry/academy/society meetings/conferences to contribute, learn, and share.

Resources

Preparation content

Shared on SLACK EAMTA-CAE

Schedule