Analog Layout

About the track

Description

In this track the students acquire basic notions of analog layout techniques, following the
goal of designing the layout of an opamp.

Track goal

The goal of this course is to provide the basis for analog layout on integrated circuits. The
design techniques discussed here provide the basis for analog layout in advance CMOS
processes. Practices will emphasize high speed techniques.

Minimum content

MOS Transistor structure (Planar, FinFET, GAAFET). IC Fabrication Flow. Introduction to
PDKs and Design Rules. Analog Layout Design Techniques. Parasitics in Analog Layout.
Design Rule Checks (DRC) & LVS. Advanced Analog Layout Topics. Testbench simulation
before and post layout. Tools & Scripting for Layout Automation

Hands-on Project

Layout of an OP AMP and post layout verification.

Professors

Eng. Agustín Ignacio Galdeman (Marvell Technology)

Agustín Ignacio Galdeman received his Electronic Engineering degree from the Instituto Tecnológico de Buenos Aires (ITBA) in 2023 and is currently pursuing a Master’s degree in Microelectronics Engineering at the University of Buenos Aires (UBA). He works as an Analog Layout Engineer at Marvell Technology, specializing in advanced FinFET nodes (N5/N3) for high-speed optical communication transceivers and mixed-signal front-end circuits. In parallel, he lectures on Algorithms and Data Structures at ITBA, where he integrates his interests in software and hardware. His previous experience includes designing the flight-control computer hardware for the student-built rocket Theros, which competed in the Spaceport America Cup 2023–2024, contributing to the development of embedded systems for autonomous flight control and telemetry.

Eng. Yesica Ayelen Ortega (Marvell Technology)

Yesica Ayelen Ortega is an Electronic Engineer who graduated in 2023 from the National Technological University – Córdoba Regional Faculty (UTN-FRC). Her connection with the institution began well before graduation, serving as a research and service fellow from 2020 to 2023. During this period, she actively contributed to academic and technical projects that strengthened her training and commitment to innovation. In 2023, she took on a teaching role in the institutional program Te ayudo a graduarte, delivering classes in Applied Electronics III. This experience allowed her to share her knowledge with students in the final stages of their academic journey. In 2024, she joined the Marvell team in the Analog Layout area, supporting the development of LRX blocks for the 3-nanometer technology node—one of the most advanced in the semiconductor industry. Thanks to her technical performance and leadership skills, she currently leads one of the main blocks of the LTX project, consolidating her position as a key figure in high-complexity analog design.

Resources

Preparation content

Shared on SLACK EAMTA-CAE